1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to cache memory hierarchies and snoop filtering circuitry for supporting coherence within such cache memory hierarchies.
2. Description of the Prior Art
It is known to provide data processing systems with cache memory hierarchies. In a non-inclusive mode of operation the cache memory hierarchy operates such that a single copy of a cache line of data is held. This single line of cache data may be held at, for example, the level one (L1), the level two (L2) or the level three (L3), but not at more than one level or in more than one cache within a level. Such non-inclusive operation makes efficient use of storage capacity within the cache hierarchy, but suffers from the disadvantage of slower access to a cache line of data when this is not stored at a location close to the transaction source requesting access to that cache line of data.
Another mode of operation is the inclusive mode. In the inclusive mode of operation a cache line of data may be stored in multiple levels of the cache hierarchy and in multiple caches within a level of the cache hierarchy. This type of operation may provide more rapid access to a given line of cache data by a requesting transaction source, but suffers from the disadvantage of less efficient usage of the storage resources of the cache hierarchy.
It is known to provide snoop filter circuitry that serves to store snoop tag values within an inclusive mode of operation that identify which cache memories are storing copies of a given cache line of data such that snoop requests and accesses may be directed to those local cache memories that are storing the cache line of data targeted. A disadvantage of snoop filter circuitry is the resource consumed in terms of gate count, power, area and the like.